The present invention relates generally to the production of ceramic substrate, glass-based, multilayer interconnect boards and, more particularly, to a method of producing such multilayer interconnect boards which utilizes laser drilling for via formation.
Ceramic substrate, glass-based, multilayer interconnect boards, generally referred to in the industry as "ceramic MIBs" or simply "MIBs" and generally referred to herein a "glass-based MIBs", are high-density printed circuit devices which are more reliable in wet environments and under elevated temperature conditions than ordinary printed circuit boards. Glass-based MIBs are particularly adapted for military applications and other applications in which high reliability, even under harsh conditions, is critical. A ceramic MIB, like an ordinary printed circuit board, comprises a plurality of interconnected circuit elements which are arranged in stacked conductor layers. Each conductor layer is separated from an adjacent conductor layer by a dielectric layer. Holes or "vias" are provided through the dielectric layers to enable connection of conductor layers.
Ordinary printed circuit boards typically employ alternating conductive layers and dielectric layers. Each conductive layer of a conventional printed circuit board typically comprises a pure metal, such as copper, which is laminated onto the surface of an underlying layer and subsequently subtractively processed (etched) into a predetermined conductor pattern. Such a conductor pattern typically has line widths and line spacing on the order of 10 mils (0.01 in.) or 250 microns (0.25 mm). Dielectric layers of ordinary printed circuit boards are typically epoxy/glass based such as FR-4 (IPC Standard) and have layer thicknesses on the order of 0.7 to 10 mils (15 to 250 microns). Laser drilling is a known method used in conventional printed circuit board production for providing holes through dielectric layers to enable connection of conductive layers. See, e.g., U.S. Pat. No. 4,829,014 of Yerman, which is hereby specifically incorporated by reference for all that is disclosed therein.
Glass-based MIBs differ from conventional printed circuit boards both in physical scale and in material composition. Glass-based MIBs comprise a high-strength, heat-resistant ceramic substrate layer which is typically aluminum oxide (Al.sub.2 O.sub.3). Conductive layers are provided by a conductive material comprising metal particles bound by a glass matrix. A conductive pattern is typically provided by silk-screen printing of the conductive material onto the surface of an underlying layer. Typical conductor pattern line width and line spacing in a glass-based MIB is on the order of 5 to 10 mils (125 to 250 microns). Each dielectric layer is also formed from a glass matrix material typically having a total layer thickness on the order of 1 to 4 mils (25 to 100 microns). Due to the fact that each conductor pattern in a glass-based MIB is, like each dielectric layer therein, formed from a glass matrix material, lasers have heretofore not been used to form vias in glass-based MIBs. It has been the general belief in the industry that any laser drilling of the dielectric layer would necessarily damage the underlying conductive layer since the two layers both comprise a glass matrix. This problem is not experienced in the laser drilling of vias for ordinary circuit boards where the underlying entirely-metal conductive layer is much more resistant to laser energy than the overlying layer of epoxy-based dielectric.
As a result of this prevailing view regarding the inapplicability of laser drilling of vias for glass-based MIBs, it is the present practice in the industry to provide vias through an exacting and expensive registration process.
FIGS. 1-3 illustrate a prior art via-forming technique which is currently used throughout the glass-based MIB fabrication industry.
As illustrated in FIG. 1, a substrate layer 10, which is typically a 25 to 60 mils (0.6 to 1.5 mm) thick layer of ceramic material, has a conductive layer 12 applied thereto in a predetermined pattern, typically by silk-screen printing. The screens used in this process are positioned at a preset elevation above the substrate layer and are adapted to elastically yield to a second preset elevation and then spring back to the original elevation in response to the passage of a conductive-material-applying squeegee thereover. The second preset elevation in conjunction with other parameters determines the thickness of the layer which is being applied. The conductor layer 12 has certain regions 13 therein which are adapted to be connected to corresponding regions in other conductive layers. These interconnect regions 13 are generally referred to in the industry as "pads". The substrate and conductive layer subassembly is then transported to a furnace where it is heat-treated or "fired" to cure and solidify the conductive layer 12. This heat-curing process typically takes on the order of 1 hour.
Next, the subassembly 100, FIG. 1, thus formed is returned to the silk-screening table where a discontinuous dielectric layer 14 having via-forming voids 16 positioned above the pad regions 13 is applied and the via-forming voids 16 filled with conductive material 30, in a series of sublayer 20, 22, 24 applications. The via fill conductive material 30 is similar in physical and mechanical properties (in the fired state) to the material used to form the dielectric layers. As illustrated in FIG. 2A, an initial sublayer 20 is applied in a silk-screening printing process. The screen used in the application of the first sublayer has blocked-out regions therein which are adapted to be placed in registry with pad regions 13 in the conductive layer and thus prevent application of dielectric material in overlying relationship with the pad regions 13. After application of the first sublayer 20, the subassembly is dried and transported to a furnace and fired to cure the dielectric material to provide a solidified sublayer. After the application and firing of the first dielectric sublayer 20, the subassembly is then returned to the silk-screening table and the via-forming voids 16 are filled with conductive material 30. Via filling is typically performed by silk-screening, using a reverse-image screen from that used to apply the dielectric sublayers. Next, the subassembly is dried and returned to the furnace and fired to cure the via fill material to provide a solidified via conductor. Next, as illustrated in FIG. 2B, a second dielectric sublayer 22 is applied in the same manner as the first dielectric sublayer, a void being provided therein directly above the pad regions 13 in the conductive layer. The second dielectric sublayer 22 is then dried and fired and the via-forming voids 18 filled, dried and fired in the same manner as the first sublayer 20. The third dielectric sublayer 24 is then applied, dried, fired, filled, dried and fired in the same manner as the second sublayer 22, thus typically completing the formation of the first dielectric layer. The primary reason that the dielectric layer 14 is applied in three successive sublayers is to facilitate creation of vias 30 (FIG. 3). The material from which the dielectric layer 14 is formed is necessarily a thixotropic material, i.e. a gelatin-like material which is capable, when under substantial mechanical shear, of flowing through a screen like a liquid but which, when not under substantial mechanical shear, has surface characteristics which cause it to resist flowing and retain a relatively straight vertical edge at formed peripheral portions thereof such as those associated with vias 16. However, such thixotropic material is, due to the stress associated with its own mass, limited in its capacity to resist lateral fluid flow and maintain an upright vertical edge. The depth of dielectric material which may be applied in a single silk-screening pass while maintaining sharp via definition is therefore limited. The maximum thickness of a dielectric sublayer having well-defined via voids therein is typically 0.7 to 1.5 mils (15 to 37 microns). The time required for the silk-screening and firing of each dielectric/via fill sublayer is typically on the order of three hours. Thus, a three-sublayer dielectric layer with via fills typically takes nine hours to complete. A four-sublayer dielectric layer takes proportionately longer.
The next step, as illustrated by FIG. 3, is to apply a second conductive layer pattern 34. The conductive pattern is again typically applied by silk-screening and has certain regions 35 therein which overlie and make conductive contact with the underlying vias 30 to form an electrical connection between the first conductive layer 12 and the second conductive layer 34.
The above-described conductive layer and dielectric layer formation and interconnection process is utilized to form a multilayer interconnect board 36 which has multiple dielectric layers 14, 15, 17, 19 and multiple conductive layers 12, 34, 35, 37 such as illustrated in FIG. 4. The last layer of the circuit board, generally referred to in the industry as the "foot print" layer, comprises a plurality of exposed connector pads 38, 40, etc., which are adapted to be attached to interfacing connectors of other electronic devices.
Although the illustrated glass-based MIB 36 comprises only four dielectric layers, some modern glass-based MIBs have as many as 15 to 24 dielectric layers which require nine hours per layer to apply. The cost associated with the application of dielectric layers typically accounts for about 50% of the total MIB production time. Due to the above described special thixotropic characteristics as well a dielectric characteristics which the fired dielectric material must possess, this material is relatively expensive and accounts for a significant portion, e.g. 60%, of the total material cost of the MIB.